1. Field of the Invention
The present invention relates to a semiconductor device, and particularly to improvement of reliability of a low-voltage MIS (insulated gate type field effect transistor) semiconductor device. More specifically, the present invention relates to improvement of the gate insulating film of an MIS transistor of a component of an MIS semiconductor memory device.
2. Description of the Background Art
In the case of a semiconductor memory device such as a DRAM (Dynamic Random Access Memory), an operating power supply voltage is lowered for high speed operation and reduced power consumption. However, a semiconductor memory device using an MIS transistor is accompanied by the following problems in lowering of a power supply voltage.
FIG. 27 is a diagram schematically showing a cross sectional structure of a memory cell of a DRAM. In FIG. 27, the memory cell includes N-type impurity regions 1002a and 1002b formed, separately from each other, on the surface of a P-type substrate region 1000, a gate-electrode layer 1005 formed above a channel region 1003 between the impurity regions 1002a and 1002b with a gate insulating film 1004 inlaid, a conductive layer 1006 connected to the N-type impurity region 1002b, and a cell plate electrode layer 1007 arranged facing the conductive layer 1006 through a capacitor insulating film (not shown).
The N-type impurity region 1002a is connected to the conductive layer 1008. The conductive layer 1008 constitutes a bit line BL, and the conductive layer 1006 and cell plate electrode layer 1007, together with a capacitor insulting film, constitute a memory cell capacitor. A cell plate voltage Vcp at an intermediate voltage level is supplied to the cell plate electrode layer 1007. The gate electrode layer 1005 constitutes a word line WL. A memory transistor is constituted of the N-type impurity regions 1002a and 1002b, gate electrode layer 1005, and substrate region 1000.
In lowering an operating power supply voltage, each parameter of a memory cell is scaled down in accordance with a predetermined scaling rule. However, to suppress a leak current between the source and drain of a memory transistor, or between the N-type impurity regions 1002a and 1002b, it is necessary to keep a threshold voltage Vtm of the memory transistor at a certain value or more. Even if an applied voltage of the gate electrode layer 1005 is equal to the ground voltage level, a current referred to as the so-called sub-threshold current flows. The sub-threshold current increases as the threshold voltage lowers in the case of an N-channel MIS transistor. Therefore, when the ground voltage is transferred to the bit line BL in accordance with data in other selected memory cell while H-level data at the power supply voltage level is stored in the N-type impurity region 1002b, the voltage level of the H-level data is lowered due to the sub-threshold current and the H-level data may be lost in the worst case. Moreover, in the case of a transistor of other peripheral circuit, the current consumption increases when a sub-threshold current increases.
It is necessary to write data at as high a voltage level as possible in a memory cell capacitor as H-level data, in order to lengthen the data retention time. Therefore, it is necessary to set a voltage level of a selected word line WL (gate electrode layer 1005) to a voltage level equal to or higher than the sum of an array power supply voltage Vcca and a threshold voltage Vtm of a memory transistor. When such a high voltage is applied to the gate electrode layer 1005, an electric field to be applied to the gate insulating film 1004 of a memory transistor increases. To prevent the dielectric breakdown of the gate insulating film due to the large electric field, it is necessary to increase the thickness of the gate insulating film 1004. Therefore, the thickness of the gate insulating film of an MIS transistor of the DRAM is determined by the thickness of the gate insulating film 1004 of the memory transistor, and it is impossible to improve the performance of a transistor of peripheral circuitry because the absolute value of a threshold voltage of a MIS transistor of the peripheral circuitry increases and a high-speed operation cannot be performed. It can be considered to make the transistor of the peripheral circuit different in thickness of the gate insulating film from the memory transistor. In this case, however, it is necessary to fabricate the peripheral transistor and the memory cell transistor in manufacturing steps different from each other and the number of fabrication steps increases.
Moreover, to raise the threshold voltage of the memory transistor, it is necessary to raise the impurity concentration (channel doping concentration) of the surface of the channel region 1003. In this case, such problems occur that an electric field (built-in electric field) applied across the PN junction between the channel region 1003 and impurity region 1002b increases. Consequently, a leak current at the PN junction increases, electric charges stored in the conductive layer 1006 are discharged, the voltage level of H-level data lowers, and the data retention characteristics deteriorates.
The following approaches have been proposed so far in order to solve the foregoing problems.
(1) Negative Voltage Word Line Scheme (Negative Word Line Scheme)
FIG. 28A is a diagram showing an electric equivalent circuit of a DRAM memory cell. In FIG. 28A, a memory cell MC includes a memory cell capacitor MS for storing information and a memory transistor MT for connecting the memory cell capacitor MS to a bit line BL in accordance with the voltage of a word line WL. Normally, bit lines BL and /BL are arranged in a pair and a memory cell is connected to either of the bit lines in the pair.
In the negative voltage word line scheme (NWL scheme), when a word line WL is held in an unselected state, it is set to a negative voltage VNN as shown in FIG. 28B. The threshold voltage of the memory transistor MT is lowered in accordance with the negative voltage VNN. Even if the threshold voltage Vtm is lowered, the negative voltage VNN is applied to the unselected word line WL and a state is realized in which the threshold voltage Vtm is equivalently high. The data in a selected memory cell is read onto the bit line BL. The bit line BL changes in voltage between the array power supply voltage Vcca (=VDH) and the ground voltage Vss (=VDL). It is assumed here that other word line is selected, L-level data is read to the bit line BL, and the bit line BL is set to the ground voltage Vss level. The unselected word line WL is kept at the negative voltage VNN level. When the memory cell MC shown in FIG. 28A is an unselected memory cell, the negative voltage VNN is applied between the gate and source of the memory transistor MT, and the word line WL enters the reverse biased state deeper than the state in the case in which the word line WL is kept at the ground voltage level. Therefore, even if the threshold voltage of the memory transistor MT is low, a sub-threshold current is completely suppressed.
Moreover, by lowering the threshold voltage Vtm, it is possible to lower the level of a voltage VCH transferred to a selected word line WL. Correspondingly, it becomes possible to decrease the thickness of the gate insulating film of the memory transistor MT. In addition, because the threshold voltage Vtm can be lowered, it is possible to lower the channel doping concentration, lower the built-in electric field of a PN junction in a channel region. Accordingly, the substrate leak current at the PN junction can be reduced to lengthen the data retention time.
(2) Boosted Sense Ground Scheme (BSG Scheme)
FIG. 29A is a diagram showing applied voltages of a word line and a bit line in accordance with the boosted sense ground scheme (hereinafter referred to as BSG scheme). As shown in FIG. 29A, in the BSG scheme, an array power supply voltage Vcca and a boosted sense ground voltage Vbsg are applied to a bit line BL as an H-level voltage VDH and an L-level voltage VDL, respectively. The boosted sense ground voltage Vbsg is slightly higher than the ground voltage Vss. The word line WL is kept at the ground voltage Vss when unselected, and set to the high voltage VCH when selected.
In the case of the BSG scheme, as shown in FIG. 29B, the boosted sense ground voltage Vbsg is applied to the bit line BL. Therefore, even if an unselected word line WL is set to the ground voltage Vss, the memory transistor has the gate and source set to a deep reverse biased state. Therefore, similarly to the case of the NWL scheme, it is possible to lower the threshold voltage Vtm of the memory transistor MT and accordingly to lower the high voltage VCH transferred to a selected word line. Thus, similarly to the case of the NWL scheme, it is possible to decrease the thickness of the gate insulating film of the memory transistor MT. Moreover, it is possible to lower the channel doping concentration of the memory transistor MT, to lengthen the data retention time.
FIG. 30 is a diagram showing applied voltages of a bit line and a word line of a conventional DRAM cell. The conventional DRAM cell includes a memory transistor MT formed of an MIS transistor having a comparatively high threshold voltage Vtm. In the conventional DRAM cell, a selected word line WL is driven up to a high voltage-Vpp level and a bit line BL changes in voltage between H-level voltage VDH and L-level voltage VDL. The L-level voltage VDL is kept at the ground voltage Vss level.
The high voltage Vpp is applied to the gate of the memory transistor of a selected memory cell. Therefore, when the bit line BL is kept at the ground voltage Vss, a voltage V1=Vpp is applied between the gate and source of the memory transistor. For an unselected memory cell, however, an unselected word line WL is kept at the ground voltage Vss level. Therefore, when the H-level voltage VDH (=array power supply voltage Vcca) is applied to the bit line BL, a voltage V2=VDH at highest is applied to a gate insulating film.
In the conventional DRAM cell, a voltage applied between the gate and source of the memory transistor of a selected memory cell becomes higher than that of the memory transistor of an unselected memory cell by a voltage xcex94Vw=Vppxe2x88x92VDH. Therefore, the reliability of a memory cell of a conventional DRAM is decided by the reliability of the gate insulating film of the transistor of the selected memory cell.
FIG. 31 is a diagram showing voltages of a word line and a bit line of an NWL scheme DRAM. In the NWL scheme, an unselected word line is kept at the negative voltage VNN level and a selected word line WL is kept at the high voltage VCH level. A bit line BL changes in voltage between array power supply voltage Vcca (=VDH) and ground voltage Vss (=VDL). For an unselected memory cell, the maximum value V1n of voltages applied between the gate and source of a memory transistor is equal to VDHxe2x88x92VNN. In the case of a selected memory cell, the maximum value V2n of voltages applied between the gate and source of a memory transistor is equal to VCH. Therefore, depending on the voltage level of the negative voltage VNN, a voltage to be applied to the gate insulating film of the memory transistor of an unselected memory cell may be higher than a voltage applied to the gate insulating film of the memory transistor of the selected memory cell. Moreover, the maximum value V1n of voltages applied between the gate and source of an unselected memory cell rises by the absolute value of the negative voltage VNN, as compared to a conventional case.
FIG. 32 is a diagram schematically showing voltages of a word line WL and a bit line BL in the BSG scheme. In FIG. 32, in the BSG scheme, a maximum voltage is applied between the gate and source of a memory transistor of a selected memory when the bit line BL is kept at the level of a low level voltage VDL (=Vbsg), and a voltage of VCHxe2x88x92Vbsg is applied between the gate and source as the maximum voltage V2b. For an unselected memory cell, the maximum value V1b of voltages applied between the gate and source of a memory transistor is equal to the voltage VDH (=Vcca) because the unselected word line WL is kept at the ground voltage Vss level. Therefore, also in this case, although voltages applied between the gates and sources of memory transistors of selected and unselected memory cells are almost the same, a voltage applied across the gate insulating film of the memory transistor of the unselected memory cell becomes higher than that of the selected memory cell.
Particularly, when the reliability of the gate insulating film of a memory transistor is considered in view of a case in which the voltage level of an unselected word line is equal to a low level voltage VDL, that is, when the reliability is considered by utilizing the voltage amplitude of VCHxe2x88x92VDL=V1 of a selected word line and the voltage amplitude of VDHxe2x88x92VDL=V2 of a bit line as parameters, it is impossible to assure the reliability of the gage insulating film of an unselected memory cell in both the NWL and BSG schemes. Particularly, a gate edge is subject to an electric field higher than that of a gate inside due to the edge effect (fringe effect), it is impossible to completely assure the reliability of the memory transistor of the unselected memory cell.
In a semiconductor memory, unselected memory cells are an overwhelmingly majority, as compared to selected memory cells. Therefore, when the oxide film reduced thickness Tox of the gate insulating film of a memory transistor MT is to be decreased, reliabilities of the gate insulating films of all the memory cells are decided by the reliabilities of the memory cells in an unselected state, and it is impossible to completely assure the reliabilities of memory cells.
Moreover, a burn-in test is normally performed to test the reliability of the gate insulating film. In the burn-in test, however, a gate voltage is accelerated with the memory cell selection state focused on. Therefore, when an electric-field stress applied to a gate insulating film of a memory cell in an unselected state is close to or exceeds that of a memory cell in a selected state, a problem occurs that it is impossible to effectively perform a burn-in test for assuring the reliability of the memory cell in the case of a conventional burn-in mode.
The problem of the gate insulating film of the transistor of the memory cell as described above is not restricted to a semiconductor memory, but a general semiconductor integrated circuit suffers from similar disadvantages. That is, when the gate to source of a transistor in the unselected state such as the standby state is set to the reverse biased state in order to reduce a leak current, the same problem occurs. Particularly, when a transistor to be turned off in the standby state in a hierarchical power supply configuration is set to the reverse biased state, an electric field applied to a gate insulating film is increased in the transistors in the standby state.
Moreover, not only in the case of a DRAM but also in other semiconductor memory (e.g. SRAM (Static Random Access Memory)), when a component is formed of an MIS transistor and a word line is driven to a negative voltage, the same problem occurs.
It is an object of the present invention to provide semiconductor integrated circuit of a high reliability.
It is another object of the present invention to provide a semiconductor integrated circuit having an improved gate insulating film reliability and operating with a low power supply voltage.
It is still another object of the present invention to provide an integrated semiconductor memory circuit device operating with a low power supply voltage and improved in reliability of gate insulating film.
It is a further object of the present invention to provide a semiconductor memory capable of easily performing burn-in of an unselected memory cell.
It is a further another object of the present invention to provide a semiconductor integrated circuit capable of easily and accurately applying burn-in to a gate insulating film in the standby state.
A semiconductor device according to the first aspect of the present invention includes a bit line for transferring a signal changing between a first voltage and a second voltage higher than the first voltage, and a memory cell having an element for storing information, and a selection gate for connecting the element to the bit line when selected. The selection gate is constituted of an insulated gate type field effect transistor.
The semiconductor device according to the first aspect of the present invention further includes a word line connected to the selection gate of the memory cell for transferring a voltage determining selection/unselection of the element and a word-line voltage applying circuit for applying a voltage to the word line. The word line voltage applying circuit applies a third voltage out of the voltage changing range of the bit line when the element is unselected and a fourth voltage when the element is selected. The third voltage is at a voltage level for setting the reliability evaluation value of the insulating film of the selected gate below that when the fourth voltage is applied.
A semiconductor device according to another aspect of the present invention includes an internal circuit having a power supply node, a power supply voltage transfer line, a power supply control transistor constituted of an insulated gate type field effect transistor, connected between the power supply node and the power supply voltage transfer line and set to a high-impedance state when the internal circuit is unselected and to a low-impedance state when the internal circuit is selected, and a control circuit for applying a control signal to the gate of the power supply control transistor in response to an operation mode designation signal designating an operation mode of the internal circuit. The control circuit applies, as the control signal, a voltage at which the reliability evaluation value of a gate insulating film of the power control transistor in the high-impedance state is equal to or less than that of the gate insulating film of the power control transistor in the low-impedance state.
A semiconductor device according to still another aspect of the present invention includes an internal circuit having a plurality of sub circuits. The sub circuits include a first sub circuit coupled to a first power line transferring a first power source voltage, and a second sub circuit coupled to a second power line transferring a second power source voltage.
The semiconductor device according to the still another aspect of the present invention further includes a first power supply circuit connected to the first power line, for generating the first power source voltage, and a second power supply circuit connected to a second power line, for generating a voltage at a first voltage level independently of selection/unselection of the internal circuit. The reliability evaluation value of the gate insulating film of a transistor of the sub-circuit when the internal circuit is unselected is set to a value equal to or less than that when the internal circuit is selected.
A reliability evaluation value is represented by a monotonously increasing function of an electric field applied to a gate insulating film, as an example. Therefore, by decreasing the reliability evaluation value, the reliability of the gate insulating film is improved. By making the reliability evaluation value of the gate insulating film of a transistor in the unselected state equal to or less than that in the selected state, the state of an MIS transistor in the unselected state does not deteriorate the reliability of the whole circuit, and it becomes possible to improve the reliability of the whole circuit. Thereby, it is possible to reduce a power supply voltage and an oxide film reduced thickness of a gate insulating film.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.